Browse packages

rivos-visni

1.0.0Readiness: RL1Packaged

by extensilica

Rivos XRivosVisni vector integer small new instructions (zero/insert/extract)

No confirmed encoding conflictsShares encoding space with 1 extension(s)
Show encoding relation details

rivos-zizip INFO

  • SHARED_MAJOR_OPCODE: opcode 0x5B — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.
  • SHARED_CUSTOM_SPACE: both declare custom-2; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

Pre-silicon bridge: this package is meant to be evaluable before RTL/FPGA/ASIC decisions.

Readiness & capabilities

Readiness: RL1Packaged

Runnable (entry declared)
Testable (testEntry declared)
Repro: bundled
Repro: resolved
Repro: host-dependent
Toolchain: bundled
Toolchain: external
Sim: Spike
Emu: QEMU
RTL
FPGA
Tests

README

Rivos XRivosVisni vector integer small new instructions (zero/insert/extract)

Version History

VersionPublishedStatus
1.0.0latest
xsil install [email protected]
May 14, 2026active

Downloads

0

Last 7 days

0

Last 30 days

0

All time

Daily downloads — last 30 days

06-1506-2206-2907-0607-1307-14

By version

1.0.0
0

Reviews

Sign in to leave a review.

No reviews yet

Be the first to leave a review.