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xthead-bb

1.0.0Readiness: RL1 — Packaged

by extensilica

T-Head XTheadBb bit-manipulation extension

No confirmed encoding conflictsShares encoding space with 11 extension(s)
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mojo-v WARNING

  • PARTIAL_DECODE_OVERLAP: opcode 0x0B funct3 0x1 funct7 null — opcode and funct3 match, but the full mask isn't known (funct7/funct12 not imported). Possible overlap; needs full mask/match data to confirm.
  • PARTIAL_DECODE_OVERLAP: opcode 0x0B funct3 0x2 funct7 null — opcode and funct3 match, but the full mask isn't known (funct7/funct12 not imported). Possible overlap; needs full mask/match data to confirm.
  • PARTIAL_DECODE_OVERLAP: opcode 0x0B funct3 0x3 funct7 null — opcode and funct3 match, but the full mask isn't known (funct7/funct12 not imported). Possible overlap; needs full mask/match data to confirm.
  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-ba WARNING

  • PARTIAL_DECODE_OVERLAP: opcode 0x0B funct3 0x1 funct7 null — opcode and funct3 match, but the full mask isn't known (funct7/funct12 not imported). Possible overlap; needs full mask/match data to confirm.
  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-bs WARNING

  • PARTIAL_DECODE_OVERLAP: opcode 0x0B funct3 0x1 funct7 null — opcode and funct3 match, but the full mask isn't known (funct7/funct12 not imported). Possible overlap; needs full mask/match data to confirm.
  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-condmov WARNING

  • PARTIAL_DECODE_OVERLAP: opcode 0x0B funct3 0x1 funct7 null — opcode and funct3 match, but the full mask isn't known (funct7/funct12 not imported). Possible overlap; needs full mask/match data to confirm.
  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-fmemidx INFO

  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-fmv INFO

  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-int INFO

  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-mac WARNING

  • PARTIAL_DECODE_OVERLAP: opcode 0x0B funct3 0x1 funct7 null — opcode and funct3 match, but the full mask isn't known (funct7/funct12 not imported). Possible overlap; needs full mask/match data to confirm.
  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-mempair INFO

  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-sync INFO

  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

xthead-vdot INFO

  • SHARED_CUSTOM_SPACE: both declare custom-0; shared custom space (no per-vendor allocation in RISC-V). Not a conflict on its own — composing both needs opcode remapping or selective enable.

Pre-silicon bridge: this package is meant to be evaluable before RTL/FPGA/ASIC decisions.

Readiness & capabilities

Readiness: RL1 — Packaged

Runnable (entry declared)
Testable (testEntry declared)
Repro: bundled
Repro: resolved
Repro: host-dependent
Toolchain: bundled
Toolchain: external
Sim: Spike
Emu: QEMU
RTL
FPGA
Tests

README

T-Head XTheadBb bit-manipulation extension

Version History

VersionPublishedStatus
1.0.0latest
xsil install [email protected]
May 14, 2026active

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06-1506-2206-2907-0607-1307-14

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1.0.0
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